This invention relates, in general, to integrated circuit packages, and more particularly, to packages containing multiple integrated circuits connected together on a shared substrate, commonly referred to as a multi-chip module.
The size, complexity, and speed of integrated circuits are increasing every year. The technology to interconnect and package integrated circuits is critical to generate benefit from the integrated circuit process and design advances. Some of the problems package designers must contend with are high input and output pin counts, power dissipation, noise, power and ground strategies, Input/Output loading (resistive, capacitive, and inductive effects), CAD requirements, burn-in/test, and package costs.
In package design, density can translate directly to speed. The trend is to develop methods to house and interconnect multiple integrated circuits in the smallest area possible. It can be a very difficult task to balance the different aspects of package design for a multi-chip carrier. This type of packaging is referred to as a multi-chip module.
It is now recognized that for cost-effective production of such multi-chip modules it is critical to burn-in and test individual components which comprise the multi-chip module prior to the multi-chip module fabrication. Full functional testing is performed after the burn-in process. Though such modules have been built by the vertically integrated system manufacturers for some time, there are still very few low cost solutions. It is also necessary to provide reliable means of replacing defective components after functional test of the module.
One style of multi-chip module uses solder bumping techniques to attach integrated circuits to a module substrate. Solder bumps are placed on the pads of the integrated circuit or module (or both). The integrated circuit is then mated to the module substrate. A thermal cycle melts the solder and bonds the pad areas together. The module substrate has interconnects to route the integrated circuit's I/O (Inputs and Outputs) to the system netlist.
The solder bump technique has advantages over other multi-chip module methods. Pad areas are not confined to the periphery of the integrated circuit. The number of pads may be increased by adding pads to the internal sections of the die. Integrated circuits can be placed in close proximity to each other on the substrate minimizing chip to chip delay. Moreover, the inductance of the solder bumps are almost an order of magnitude smaller than other standard interconnection methods (for example wire-bonding or TAB) increasing system performance. Exotic materials are not used in the process. Solder bumping has proven a manufacturable process that is cost effective and reliable for multi-chip modules.
The conventional solder bump approach does not address all package requirements. Test is an extremely important issue for multi-chip modules. How the testing is approached can have a direct impact on project development time, test complexity, tester time, test quality, and module cost. It is imperative to keep multi-chip module final test failures to an absolute minimum. Module cost may be expensive enough to justify rework on any system with defective parts. The conventional test method employed consists of parametric and functional testing of the unpackaged integrated circuits at wafer probe, the good parts are sorted out, then attached to the module substrate, life cycle tests are run on the module, and a final test to prove system integrity. Burn-in of the unpackaged integrated circuit is difficult to implement and is often not carried out. The flaw with this approach is the likelihood of an integrated circuit failing after the multi-chip module has been built. Also, the final test of the module to insure that the system functions correctly can be extremely complex and time consuming. This increases both development time and cost.
Another aspect of multi-chip modules incorporating densely packed high power integrated circuits is that efficient heat dissipation is required. The amount of power dissipated by the system is dependent on the process technology and the type of circuitry used. As integrated circuits are placed closer together the power dissipation problem becomes aggravated. In the conventional solder bump interconnection technology the only contact the integrated circuits have to the module substrate is through the solder bumps but heat dissipation through the solder bumps is not an ideal solution. Thermal bumps for increased heat dissipation can be added to the integrated circuits at the cost of active area. The heat generated by the integrated circuits is more efficiently dissipated into the ambient by way of the back plane of the integrated circuit. For multi-chip modules that need better thermal dissipation capabilities, complex attachments such as thermal conduction modules incorporating heat sinking or forced air is used. This increases the complexity of the module and adds to the cost.
Solder bumping is performed at a wafer level. The steps must be controlled to insure the proper size and uniformity of the solder bumps. The technology to bump individual die is not readily available at this time. If a semiconductor manufacturer wants to supply integrated circuits for a multi-chip module, facilities must be set up for in-house solder bumping or arrangements for third-party bumping would be needed. Since the size and uniformity of the solder bumps are critical to the module assembly process, it would be desirable if this was under the control of a single group in the module manufacturing process. Also, having the ability to handle individual integrated circuit die would allow many suppliers to compete as a source of components.
Most of these issues can be tied into increased manufacturing costs and extended multi-chip module development time. Accordingly, it would be desirable to provide a multi-chip module which overcomes the deficiencies of the prior art.